Magnetoresistive random access memory (MRAM) is a non-volatile memory technology that uses magnetic elements. MRAM is gaining popularity as the next-generation memory technology for numerous semiconductor device applications which require low cost and high speed. Several types of MRAM are well known in the art, and MRAM operation can be briefly explained using the example of a commonly used variety of MRAM, a Spin Transfer Torque MRAM (STT-MRAM). A STT-MRAM uses electrons that become spin-polarized as the electrons pass through a thin film (spin filter).
FIG. 1 illustrates a conventional STT-MRAM bit cell 100. The STT-MRAM bit cell 100 includes magnetic tunnel junction (MTJ) storage element 105 (also referred to as “MTJ stack” or simply, “MTJ”), transistor 101, bit line 102 and word line 103. MTJ 105 is formed, for example, from pinned layer 124 and free layer 120, each of which can hold a magnetic moment or polarization, separated by insulating tunneling barrier layer 122. There may be an anti-ferromagnetic (AFM) layer and a cap layer (not shown) in MTJ 105. The AFM layer is used to pin the magnetic moment of the pinned layer. The cap layer is used as a buffer layer between the MTJ and metal interconnects. The polarization of the free layer can be reversed by applying current in a specific direction such that the polarity of the pinned layer and the free layer are either substantially aligned or opposite. The resistance of the electrical path through the MTJ varies depending on the alignment of the polarizations of the pinned and free layers. This variation in resistance can be used to program and read STT-MRAM bit cell 100, as is known. STT-MRAM bit cell 100 also includes circuit elements, source line 104, sense amplifier 108, read/write circuitry 106 and bit line reference 107. Those skilled in the art will appreciate the operation and construction of STT-MRAM bit cell 100 as known in the art.
As seen from the above example, the fabrication of a conventional STT-MRAM bit cell involves integration of the various above-described components on a circuit board or semiconductor package. More specifically, memory or storage elements (e.g., MTJ 105) may be integrated with various other circuit elements (generally referred to herein, as, “logic elements”) such as, passive components, metal wires, vias, transistors, logic gates, etc. In general, such integration requires process compatibility between the memory elements and the logic elements. Several challenges arise in this area, particularly as device technology continues to advance towards smaller and smaller device sizes.
For example, during the fabrication of MRAM devices such as STT-MRAM bit cell 100, it is important to ensure that capacitance (C) of various components and resistance (R) of various components and connections are maintained at low values. This is important for reducing cross coupling and RC delay values.
However, dielectric material, conventionally referred to as interlayer dielectric (ILD) material or inter-metal dielectric (IMD) material, used for integrating dense metal levels or metal layers required at advanced device nodes, may require using low-K or extreme low-K (ELK) dielectric materials with a view to lowering parasitic capacitance. Lowering the dielectric constant is conventionally accomplished by inserting light weight elements to reduce the silicon-oxide bond density, which is in turn conventionally associated with degraded mechanical stability.
Several additional Chemical mechanical polishing (CMP) process steps are used in conventional manufacture of MRAM devices. These additional CMP steps before the fabrication of Cu interconnect structures require a high level of mechanical stability, which may not be compatible with the use of low-K or ELK dielectric materials. The conventional approaches do not effectively balance the conflicting effects of the K-value of dielectric materials on parasitic capacitance and mechanical stability. Further, such low-K dielectric materials may require high-temperatures (e.g., 400 C.) for ultraviolet (UV) curing, which may cause degradation of the MRAM devices such as MTJ 100.
Moreover, integrating MRAM devices in advanced logic nodes (e.g., 28 nm and below) with logic processes such as complementary metal oxide semiconductor (CMOS) back end of line (BEOL) processes, introduces additional challenges. Vias are conventionally used for connecting elements between different layers of interconnections. The separation between adjacent layers, which relates to a vertical height of the vias may be different from that of the MRAM elements such as MTJ 100. The maximum via height may be limited by aspect ratio specifications whereas the minimum MTJ height may be limited by CMP tolerances. Thus, there may be mismatches between the via heights and MTJ heights which may frustrate integration of these elements on a common device.
Accordingly, there is a need in the art for avoiding the aforementioned conventional approaches for integration of MRAM devices.